Original technical submissions on, but not limited to, the following topics are invited:

SYSTEM-LEVEL CAD

1.1 System Design

System-level specification, modeling, simulation, design flows

System-level issues for 3D integration

System-level design case studies and applications

HW/SW co-design, co-simulation, co-optimization, and co-exploration, platforms for emulation and rapid prototyping

Micro-architectural transformation

Multi-/many-core processor, GPU and heterogeneous SoC

Memory and storage architecture and system synthesis

System communication architecture, Network-on-chip design

Modeling, simulation, high-level synthesis, power/performance analysis, programming of heterogeneous computing platforms

Application driven system design for big data

Analysis and optimization of data centers

1.2 Embedded, Cyber-Physical (CPS), IoT

Systems and Software

AI and machine learning for embedded systems

HW/SW co-design for embedded systems

Compute, memory, storage, interconnect for embedded systems

Domain-specific accelerators

Energy/power management and energy harvesting

Real-time software and systems

Middleware, virtual machines, and runtime support

Dependable, safe, secure, trustworthy embedded systems

Embedded software: compilation, optimization, testing

CAD for IoT, edge and fog computing

Modeling, analysis, verification of CPS systems

Green computing (smart grid, energy, solar panels, etc.)

CAD for application domains including wearables, health care, autonomous systems, smart cities

1.3 Neural Networks and Deep Learning

Hardware and architecture for neural networks

Compilers for deep neural networks

Design method for learning on a chip

System-level design for (deep) neural computing

Neural network acceleration including GPU and ASICs

Safe and secure machine learning

Hardware accelerators for Artificial Intelligence

1.4 Reconfigurable Computing

Novel reconfigurable architectures (FPGA, CGRA, etc.)

Neural network acceleration on reconfigurable accelerators

High-level synthesis on reconfigurable architectures

Compilers for reconfigurable architectures

Reconfigurable fabric security

HW/SW prototyping and emulation on FPGAs

Post-synthesis optimization for FPGAs

FPGA-based prototyping for analog, mixed-signal, RF systems

1.5 Hardware Security, Security Architecture and Systems

Hardware Trojans, side-channel attacks, fault attacks and countermeasures

New physical attack vectors or methods for ASICs

Nano electronic security

Hardware-based security (CAD for PUF’s, RNG, AES etc.)

Split Manufacturing for security

Supply chain security and anti-counterfeiting

Artificial Intelligence for attack prevention systems

Design and CAD for security

Security implications of CAD

Trusted execution environments

Privacy-preserving computation

Cloud Computing data security

Sensor network security

1.6 Low Power and Approximate Computing in System Design

Power and thermal estimation, analysis, optimization, and management techniques for hardware and software systems

Energy- and thermal-aware application mapping and scheduling

Energy- and thermal-aware architectures, algorithms

Energy- and thermal-aware dark silicon system design

Hardware techniques for approximate/stochastic computing

SYNTHESIS, VERIFICATION, PHYSICAL DESIGN, ANALYSIS, SIMULATION, AND MODELING

2.1 High-Level, Behavioral, and Logic Synthesis and Optimization

High-level/Behavioral/Logic synthesis

Technology-independent optimization and technology mapping

Functional and logic timing ECO (engineering change order)

Resource scheduling, allocation, and synthesis

Interaction between logic synthesis and physical design

2.2 Testing, Validation, Simulation, and Verification

High-level/Behavioral/Logic modeling, validation, simulation

Formal, semi-formal, and assertion-based verification

Equivalence and property checking

Emulation and hardware simulation/acceleration

Post-silicon validation and debug

Digital fault modeling and simulation

Delay, current-based, low-power test

ATPG, BIST, DFT, and compression

Memory test and repair

Core, board, system, and 3D IC test

2.3 Cell-Library Design, Partitioning, Floorplanning, Placement

Cell-library design and optimization

Transistor and gate sizing

High-level physical design and synthesis

Estimation and hierarchy management

2D and 3D partitioning, floorplanning, and placement

Post-placement optimization

Buffer insertion and interconnect planning

2.4 Clock Network Synthesis, Routing, and Post-Layout Optimization and Verification

2D and 3D clock network synthesis

2D and 3D global and detailed routing

Package-/Board-level

Chip-package-board co-design

Post-layout/-silicon optimization

Layout and routing issues for optical interconnects

2.5 Design for Manufacturability and Design for Reliability

Process technology characterization, extraction, and modeling

CAD for design/manufacturing interfaces

CAD for reticle enhancement and lithography-related design

Variability analysis and statistical design and optimization

Yield estimation and design for yield

Physical verification and design rule checking

Machine learning for smart manufacturing and process control

Analysis and optimization for device-level reliability issues

Analysis optimization for interconnect reliability issues

Reliability issues related to soft errors

Design for resilience and robustness

2.6 Timing, Power and Signal Integrity Analysis and Optimization

Deterministic and statistical static timing analysis, optimization

Power and leakage analysis and optimization

Circuit and interconnect-level low power design issues

Power/ground network analysis and synthesis

Signal integrity analysis and optimization

2.7 CAD for Analog/Mixed-Signal/RF and Multi-Domain Modeling

Analog, mixed-signal, and RF noise modeling, simulation, test

Electromagnetic simulation and optimization

Device, interconnect and circuit extraction and simulation

Behavior modeling of devices and interconnect

Package modeling and analysis

Modeling of complex dynamical systems (molecular dynamics, fluid dynamics, computational finance, etc.)

CAD FOR EMERGING TECHNOLOGIES, PARADIGMS

3.1 Bio-inspired and Neuromorphic Computing, Biological Systems and Electronics, and New  Computing Paradigms

Network and neuron models

Devices and hardware for neuromorphic computing

Non-von Neumann architectures

PEvent or spike-based hardware systems

CAD for biological computing systems

CAD for synthetic biology

CAD for bio-electronic devices, bio-sensors, MEMS Systems

3.2 Nanoscale and Post-CMOS Systems

 New device structures and process technologies

New memory technologies (flash, PCM, STT-RAM, memristor)

Nanotechnologies, nanowires, nanotubes, graphene, etc.

Quantum computing

CAD for mixed-domain (semiconductor, nanoelectronic, MEMS, and electro-optical) devices, circuits, and systems

CAD for nanophotonics and optical devices/ communication

DFM and reliability issues for emerging devices (3D, Nanophotonics, non-volatile logic/memory, etc.)

Device, interconnect and circuit extraction and simulation

Behavior modeling of devices and interconnect

Package modeling and analysis

Modeling of complex dynamical systems (molecular dynamics, fluid dynamics, computational finance, etc.)