The workshop will cover various aspects of VLSI-related silicon nanoelectronics. Areas of interest include, but are not limited to:

• Sub-10 nm transistors employing conventional and novel architecture including non-classical structures, novel channel and source/drain materials, non-thermal injection mechanisms
• Device physics of nanodevices including quantum effects, nonequilibrium and ballistic transport
• Modeling and simulation of nanoscale devices
• Extreme processing of nanostructures, including nanopatterning
• Junction and insulator materials and process technology for nanodevices
• Nanoscale surface, interface, and heterojunction effects in nanodevices
• Device scaling issues including doping fluctuations and atomic granularity
• Novel architectures for nanodevices including quantum computing
• Optoelectronics using silicon nanostructures
• Devices for heterogeneous integration on silicon, including 2D materials, Ge and III-V, CNT, spin-based devices, MEMs and NEMS, etc.
• Environmental devices which contribute to low-carbon society (wireless sensors, energy harvestors, steep slope devices, etc.)